With the recent tendencies for electronic equipment to have a smaller size and higher performance, it has been demanded for semiconductor devices constituting electronic equipment and printed circuit boards for mounting the devices to have reduced size and thickness, higher performance and higher reliability. To meet these demands, pin insertion mount is being displaced by surface mount, and, in recent years, a surface mount technology called bare chip mount has been under study, in which non-packaged (bare) semiconductor elements are directly mounted on a printed circuit board.
In bare chip mounting, however, because silicon chips having a thermal expansion coefficient of 3 to 4 ppm/.degree. C. are directly mounted on a printed circuit board having a thermal expansion coefficient of 10 to 20 ppm/.degree. C., stress is developed due to the difference in thermal expansion to impair the reliability. The stress causes joint fracture in, for example, flip chip bonding, which will lead to a faulty electrical connection.
In order to relax the thermal stress, it has been practiced to fill the gap between a mounted semiconductor element and a printed circuit board with an adhesive called an underfilling material thereby to disperse the stress imposed to the joint. In order for the stress to be absorbed by the printed circuit board itself, a multilayer printed circuit board having shear stress-absorbing layers between circuit layers to provide a stepwise gradation of thermal expansion coefficient in its thickness direction has been proposed (see JP-A-7-297560). However, reliability achieved by these techniques is still insufficient. It is indispensable for securing further improved reliability to diminish the thermal expansion coefficient of the printed circuit board itself.
In this connection, JP-A-61-212096 teaches a multilayer circuit board comprising an Fe--Ni alloy substrate having alternately formed thereon insulating layers and wiring conductors and, if desired, having solder pads formed on the top layer thereof by photoetching, the substrate, the insulating layers and the wiring conductors being united into an integral laminate by pressure bonding under heat. The technique disclosed has the following disadvantages. Where copper is used as a wiring conductor, it is difficult to reduce the thermal expansion coefficient of the whole circuit board to the level of silicon because the elastic modulus of copper is far greater than that of a polyimide resin used as an insulating layer. The wiring conductor is formed by thin metallic film formation techniques, such as vacuum deposition and sputtering, which have low productivity and incurs increased cost. Formation of solder pads by deposition followed by photoetching requires complicated steps.
On the other hand, the increasing I/O pin count of semiconductors to be mounted has increased the necessity of laminating a plurality of circuit boards. A multilayer circuit board can be produced by a build up method comprising alternately building up, on one or both sides of a substrate, insulating layers of a photosensitive resin and conductor layers formed by plating or deposition. The build up method is disadvantageous in that the production process is complicated and involves many steps, the yield is low, and much time is required.
JP-A-8-288649 proposes a method for producing a multilayer circuit board comprising forming protrusions of conductive paste by means of a dispenser, etc. on the copper side of a single-sided copper-clad epoxy/glass laminate, pressing an adhesive sheet and copper foil thereto, and repeating these steps. This technique is unsatisfactory in reliability of electrical connection, connection resistivity, and the like, and is hardly applicable to fine circuits. Further, it is a time-consuming method that the step of pressing must be repeated as many times as the number of the layers.
The inventors of the present invention have found that the above-described problems associated with conventional techniques are chiefly caused by the extremely greater thermal expansion of the board, more specifically, the organic materials making up the insulating layer, such as an epoxy resin and a polyimide resin, and copper as a wiring material, than that of semiconductor elements. Copper, which is commonly used as a wiring conductor, has not only a large thermal expansion coefficient but a large modulus of elasticity to increase the stress of thermal expansion. Notwithstanding, copper is an excellent electrically conductive material and has come to be indispensable as a wiring material.